Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication

Dong Wang, Seiichiro Ii, Ken Ichi Ikeda, Hideharu Nakashima, Hiroshi Nakashima

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抜粋

Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

元の言語英語
ホスト出版物のタイトルICSICT-2006
ホスト出版物のサブタイトル2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
ページ2193-2195
ページ数3
DOI
出版物ステータス出版済み - 8 2 2007
イベントICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, 中国
継続期間: 10 23 200610 26 2006

その他

その他ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
中国
Shanghai
期間10/23/0610/26/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • これを引用

    Wang, D., Ii, S., Ikeda, K. I., Nakashima, H., & Nakashima, H. (2007). Photoluminescence evaluation of defects generated during temperature ramp-up process of SiGe-on-insulator virtual substrate fabrication. : ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 2193-2195). [4098665] https://doi.org/10.1109/ICSICT.2006.306678