Possibilities to miss predicting timing errors in canary flip-flops

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida

研究成果: 著書/レポートタイプへの貢献会議での発言

5 引用 (Scopus)

抜粋

Deep submicron technologies increase parameter variations, which will make microprocessor designs very difficult, since every variation requires a large safety margin for achieving specified timing yield. This means higher supply voltage, which results in large energy consumption. Razor flip-flop (FF) is a clever technique to eliminate the supply voltage margin by exploiting circuit-level timing speculation. It combines dynamic voltage scaling technique with the error detection and recovery mechanism. We are studying an alternative timing-error-predicting FF, named canary FF. This paper discusses a critical issue regarding the canary FF. Detailed gate- and architectural-level co-simulations unveil that canary FF occasionally misses predicting timing errors.

元の言語英語
ホスト出版物のタイトル54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOI
出版物ステータス出版済み - 10 13 2011
イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, 大韓民国
継続期間: 8 7 20118 10 2011

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷物)1548-3746

その他

その他54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
大韓民国
Seoul
期間8/7/118/10/11

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Kunitake, Y., Sato, T., Yasuura, H., & Hayashida, T. (2011). Possibilities to miss predicting timing errors in canary flip-flops. : 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026656] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026656