Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

13 被引用数 (Scopus)

抄録

Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.

本文言語英語
ホスト出版物のタイトルIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
ページ217-222
ページ数6
DOI
出版ステータス出版済み - 9 19 2011
イベント17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, 日本
継続期間: 8 1 20118 3 2011

出版物シリーズ

名前Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(印刷版)1533-4678

その他

その他17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
国/地域日本
CityFukuoka
Period8/1/118/3/11

All Science Journal Classification (ASJC) codes

  • 工学(全般)

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