Power-aware test generation for reducing yield loss risk in at-speed scan testing

Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抜粋

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing without the need of any circuit modification. However, the effect achieved by previous X-filling methods for reducing launch switching activity may be far from optimal. In addition, some of them are not scalable. This paper proposes a new X-filling method based on the genetic algorithm (GA). Experimental results on benchmark circuits demonstrate the effectiveness and scalability of the new X-filling method for reducing launch switching activity.

元の言語英語
ホスト出版物のタイトルECS Transactions - ISTC/CSTIC 2009 (CISTC)
ページ231-236
ページ数6
エディション1 PART 1
DOI
出版物ステータス出版済み - 12 1 2009
イベントISTC/CSTIC 2009 (CISTC) - Shanghai, 中国
継続期間: 3 19 20093 20 2009

出版物シリーズ

名前ECS Transactions
番号1 PART 1
18
ISSN(印刷物)1938-5862
ISSN(電子版)1938-6737

その他

その他ISTC/CSTIC 2009 (CISTC)
中国
Shanghai
期間3/19/093/20/09

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • これを引用

    Yamato, Y., Wen, X., Miyase, K., Furukawa, H., & Kajihara, S. (2009). Power-aware test generation for reducing yield loss risk in at-speed scan testing. : ECS Transactions - ISTC/CSTIC 2009 (CISTC) (1 PART 1 版, pp. 231-236). (ECS Transactions; 巻数 18, 番号 1 PART 1). https://doi.org/10.1149/1.3096455