抄録
This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. Power-Pro architecture has following two functionalities, (i) Supply voltage and clock frequency can be dynamically varied, (ii) Active data-path width can be dynamically adjusted to requirement of application programs. For the application programs which require less performance or less data-path width, Power-Pro architecture realize dramatic power reduction.
本文言語 | 英語 |
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ページ | 321-322 |
ページ数 | 2 |
出版ステータス | 出版済み - 12月 1 1998 |
イベント | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn 継続期間: 2月 10 1998 → 2月 13 1998 |
会議
会議 | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
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City | Yokohama, Jpn |
Period | 2/10/98 → 2/13/98 |
!!!All Science Journal Classification (ASJC) codes
- コンピュータ サイエンスの応用
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学