Practical challenges in logic BIST Implementation - Case studies

Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung Terng Wang, Hao Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

1 被引用数 (Scopus)

抄録

TurboBIST-Logic (TBL) is a software tool suite for incorporating logic built-in self-test (BIST) technology into digital Integrated Circuits and has been used by a variety of industrial designs globally since 2002. This abstract describes major features of TBL, and uses three industrial cases to show practical issues encountered and solved over the years. It also discusses an important new trend in going "hybrid," a flexible combination of capture-clocking schemes, with the goal to achieve an ever more optimal result over stand-alone schemes. Each of the three cases had its unique requirements for logic BIST, some needing to customize an existing solution, but all were set to achieve common BIST goals of at-speed testing, simple test interface to/from ATE, low test cost, high product reliability, and repeat testability investment reuse from IC, board, system, to in-field diagnosis.

本文言語英語
ホスト出版物のタイトルProceedings of the 17th Asian Test Symposium, ATS 2008
ページ数1
DOI
出版ステータス出版済み - 12 1 2008
イベント17th Asian Test Symposium, ATS 2008 - Sapporo, 日本
継続期間: 11 24 200811 27 2008

出版物シリーズ

名前Proceedings of the Asian Test Symposium
ISSN(印刷版)1081-7735

その他

その他17th Asian Test Symposium, ATS 2008
Country日本
CitySapporo
Period11/24/0811/27/08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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