Practical test architecture optimization for system-on-a-chip under floorplanning constraints

Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

1 引用 (Scopus)

抜粋

In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic components to build SOCs, are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via TAMs, test stimuli and test responses for cores have to be transported over these TAMs. There is often the difference between the numbers of input/output ports of cores and the widths of TAMs. This difference causes the serialization of test patterns. It is probable that some parts of TAMs are unused because of the difference. This is a wasteful usage of TAMs. Test scheduling should be done in order to remove such a wasteful usage of TAMs. In this paper, a novel and practical test architecture optimization is proposed such that test time is minimized with floorplanning constraints abided. In this proposal, the computation time for the optimization can be alleviated by floorplanning manipulation. Several experimental results to this optimization are shown to validate this proposal using a commercial LP solver.

元の言語英語
ホスト出版物のタイトルProceedings - IEEE Computer Society Annual Symposium on VLSI
ホスト出版物のサブタイトルEmerging Trends in VLSI Systems Design
編集者A. Smailagic, M. Bayoumi
ページ179-184
ページ数6
DOI
出版物ステータス出版済み - 9 24 2004
イベントProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, 米国
継続期間: 2 19 20042 20 2004

出版物シリーズ

名前Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

その他

その他Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
米国
Lafayette, LA
期間2/19/042/20/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • これを引用

    Sugihara, M., Murakami, K., & Matsunaga, Y. (2004). Practical test architecture optimization for system-on-a-chip under floorplanning constraints. : A. Smailagic, & M. Bayoumi (版), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 179-184). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339527