Pre-route power analysis techniques for SoC

Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

1 引用 (Scopus)

抜粋

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets (2) Use of layout information (actual net capacitance and input signal transition time) The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

元の言語英語
ページ(範囲)686-692
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E86-A
発行部数3
出版物ステータス出版済み - 1 1 2003

    フィンガープリント

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

Yamada, T., Sakamoto, T., Furuichi, S., Mukuno, M., Matsushita, Y., & Yasuura, H. (2003). Pre-route power analysis techniques for SoC. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E86-A(3), 686-692.