Process design of superjunction MOSFETs for high drain current capability and low on-resistance

研究成果: Contribution to journalConference article

5 引用 (Scopus)

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This paper reports that the process design to cope with both high drain current density and low on-resistance in the superjunction (SJ) MOSFET. The SJ structure is attractive to reduce the specific on-resistance dramatically due to the charge compensation concept. The drain saturation current density, however, is limited by JFET depletion at bottom region of the SJ structure. This is an obstacle to shrink the chip area due to low drain current capability, even if the on-resistance can be reduced by the lateral SJ pitch narrowing. Since the SJ structure depletion is determined by the column active doping density, the SJ process design strongly affects the saturation current density and the on-resistance. The process margin cut and high doping efficiency are key factors for the compatibility between the increase of saturation drain current density and the on-resistance reduction in SJ-MOSFET.

元の言語英語
記事番号7988882
ページ(範囲)475-478
ページ数4
ジャーナルProceedings of the International Symposium on Power Semiconductor Devices and ICs
DOI
出版物ステータス出版済み - 1 1 2017
外部発表Yes
イベント29th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2017 - Sapporo, 日本
継続期間: 5 28 20176 1 2017

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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