This paper reports that the process design to cope with both high drain current density and low on-resistance in the superjunction (SJ) MOSFET. The SJ structure is attractive to reduce the specific on-resistance dramatically due to the charge compensation concept. The drain saturation current density, however, is limited by JFET depletion at bottom region of the SJ structure. This is an obstacle to shrink the chip area due to low drain current capability, even if the on-resistance can be reduced by the lateral SJ pitch narrowing. Since the SJ structure depletion is determined by the column active doping density, the SJ process design strongly affects the saturation current density and the on-resistance. The process margin cut and high doping efficiency are key factors for the compatibility between the increase of saturation drain current density and the on-resistance reduction in SJ-MOSFET.
|ジャーナル||Proceedings of the International Symposium on Power Semiconductor Devices and ICs|
|出版ステータス||出版済み - 1月 1 2017|
|イベント||29th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2017 - Sapporo, 日本|
継続期間: 5月 28 2017 → 6月 1 2017
!!!All Science Journal Classification (ASJC) codes