Programmable power management architecture for power reduction

Tohru Ishihara, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

8 引用 (Scopus)

抄録

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

元の言語英語
ページ(範囲)1473-1479
ページ数7
ジャーナルIEICE Transactions on Electronics
E81-C
発行部数9
出版物ステータス出版済み - 1 1 1998

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Clocks
Electric potential
Microprocessor chips
Electric power utilization
Power management

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Programmable power management architecture for power reduction. / Ishihara, Tohru; Yasuura, Hiroto.

:: IEICE Transactions on Electronics, 巻 E81-C, 番号 9, 01.01.1998, p. 1473-1479.

研究成果: ジャーナルへの寄稿記事

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