Rapid design space exploration of a reconfigurable instruction-set processor

Farhad Mehdipour, Hamid Noori, Inoue Koji, Kazuaki Murakami

研究成果: Contribution to journalArticle査読

抄録

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications' characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO**) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

本文言語英語
ページ(範囲)3182-3192
ページ数11
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E92-A
12
DOI
出版ステータス出版済み - 12 2009

All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 応用数学
  • 信号処理

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