Reducing dynamic power and leakage power for embedded systems

研究成果: 著書/レポートタイプへの貢献会議での発言

1 引用 (Scopus)

抄録

This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.

元の言語英語
ホスト出版物のタイトルProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
編集者John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
出版者Institute of Electrical and Electronics Engineers Inc.
ページ291-295
ページ数5
ISBN(電子版)0780374940
DOI
出版物ステータス出版済み - 1 1 2002
イベント15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, 米国
継続期間: 9 25 20029 28 2002

出版物シリーズ

名前Proceedings of the Annual IEEE International ASIC Conference and Exhibit
2002-January
ISSN(印刷物)1063-0988

その他

その他15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
米国
Rochester
期間9/25/029/28/02

Fingerprint

Embedded systems
Tuning
Data storage equipment
Experiments

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

Cao, Y., & Yasuura, H. (2002). Reducing dynamic power and leakage power for embedded systems. : J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (版), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 291-295). [1158073] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; 巻数 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158073

Reducing dynamic power and leakage power for embedded systems. / Cao, Yun; Yasuura, Hiroto.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. 版 / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 291-295 1158073 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; 巻 2002-January).

研究成果: 著書/レポートタイプへの貢献会議での発言

Cao, Y & Yasuura, H 2002, Reducing dynamic power and leakage power for embedded systems. : J Chickanosky, RK Krishnamurthy & PR Mukund (版), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158073, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 巻. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 291-295, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, 米国, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158073
Cao Y, Yasuura H. Reducing dynamic power and leakage power for embedded systems. : Chickanosky J, Krishnamurthy RK, Mukund PR, 編集者, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 291-295. 1158073. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). https://doi.org/10.1109/ASIC.2002.1158073
Cao, Yun ; Yasuura, Hiroto. / Reducing dynamic power and leakage power for embedded systems. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. 編集者 / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 291-295 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).
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