Reduction of charge build-up during reactive ion etching by using silicon-on-insulator structures

Kiyoshi Arita, Masashi Akamatsu, Tanemasa Asano

研究成果: Contribution to journalArticle査読

3 被引用数 (Scopus)

抄録

The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabrication on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed.

本文言語英語
ページ(範囲)1505-1508
ページ数4
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
36
3 SUPPL. B
DOI
出版ステータス出版済み - 3 1997

All Science Journal Classification (ASJC) codes

  • 工学(全般)
  • 物理学および天文学(全般)

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