In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.
|ジャーナル||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|出版物ステータス||出版済み - 10 1 2003|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering