Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

6 引用 (Scopus)

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In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the Individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.

元の言語英語
ページ(範囲)951-954
ページ数4
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
11
発行部数5
DOI
出版物ステータス出版済み - 10 1 2003

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All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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