Register file energy reduction by operand data reuse

Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抜粋

This paper presents an experimental study of register file utilization in conventional RISC-type data path architecture to determine benefits that we can expect to achieve by eliminating unnecessary register file reads and writes. Our analysis shows that operand bypassing, enhanced for operand-reuse can discard the register file accesses up to 65% as a peak and by 39% on average for tested benchmark programs.

元の言語英語
ホスト出版物のタイトルIntegrated Circuit Design
ホスト出版物のサブタイトルPower and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
編集者Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
出版者Springer Verlag
ページ278-288
ページ数11
ISBN(印刷物)9783540441434
DOI
出版物ステータス出版済み - 1 1 2002
イベント12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, スペイン
継続期間: 9 11 20029 13 2002

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2451
ISSN(印刷物)0302-9743
ISSN(電子版)1611-3349

その他

その他12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
スペイン
Seville
期間9/11/029/13/02

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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  • これを引用

    Takamura, H., Inoue, K., & Moshnyaga, V. G. (2002). Register file energy reduction by operand data reuse. : B. Hochet, A. J. Acosta, & M. J. Bellido (版), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings (pp. 278-288). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 2451). Springer Verlag. https://doi.org/10.1007/3-540-45716-x_28