Routing methodology for minimizing interconnect energy dissipation

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

研究成果: ジャーナルへの寄稿Conference article

抄録

In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.

元の言語英語
ページ(範囲)120-123
ページ数4
ジャーナルProceedings of the IEEE Great Lakes Symposium on VLSI
出版物ステータス出版済み - 7 28 2003
イベントProceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, 米国
継続期間: 4 28 20034 29 2003

Fingerprint

Energy dissipation
Crosstalk
Image processing
Networks (circuits)
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

これを引用

Routing methodology for minimizing interconnect energy dissipation. / Sakai, Atsushi; Yamada, Takashi; Matsushita, Yoshifumi; Yasuura, Hiroto.

:: Proceedings of the IEEE Great Lakes Symposium on VLSI, 28.07.2003, p. 120-123.

研究成果: ジャーナルへの寄稿Conference article

@article{08d16bdeb67d4a4a8d29ab68fc7c39b4,
title = "Routing methodology for minimizing interconnect energy dissipation",
abstract = "In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10{\%} maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.",
author = "Atsushi Sakai and Takashi Yamada and Yoshifumi Matsushita and Hiroto Yasuura",
year = "2003",
month = "7",
day = "28",
language = "English",
pages = "120--123",
journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",
issn = "1066-1395",
publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - Routing methodology for minimizing interconnect energy dissipation

AU - Sakai, Atsushi

AU - Yamada, Takashi

AU - Matsushita, Yoshifumi

AU - Yasuura, Hiroto

PY - 2003/7/28

Y1 - 2003/7/28

N2 - In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.

AB - In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.

UR - http://www.scopus.com/inward/record.url?scp=0038037496&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038037496&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038037496

SP - 120

EP - 123

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

SN - 1066-1395

ER -