Routing methodology for minimizing interconnect energy dissipation

Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura

研究成果: ジャーナルへの寄稿会議記事査読

抄録

In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, coupling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.

本文言語英語
ページ(範囲)120-123
ページ数4
ジャーナルProceedings of the IEEE Great Lakes Symposium on VLSI
出版ステータス出版済み - 2003
イベントProceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, 米国
継続期間: 4月 28 20034月 29 2003

!!!All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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