Satsuki

An integrated processor synthesis and compiler generation system

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

11 引用 (Scopus)

抄録

Entire systems on a chip(SOCs)embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16word register file.

元の言語英語
ページ(範囲)1373-1381
ページ数9
ジャーナルIEICE Transactions on Information and Systems
E79-D
発行部数10
出版物ステータス出版済み - 1996
外部発表Yes

Fingerprint

Computer peripheral equipment
Application programs
Computer hardware
Costs
Computer systems
Data storage equipment
Experiments
High level synthesis

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

これを引用

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., & Yasuura, H. (1996). Satsuki: An integrated processor synthesis and compiler generation system. IEICE Transactions on Information and Systems, E79-D(10), 1373-1381.

Satsuki : An integrated processor synthesis and compiler generation system. / Shackleford, Barry; Yasuda, Mitsuhiro; Okushi, Etsuko; Koizumi, Hisao; Tomiyama, Hiroyuki; Yasuura, Hiroto.

:: IEICE Transactions on Information and Systems, 巻 E79-D, 番号 10, 1996, p. 1373-1381.

研究成果: ジャーナルへの寄稿記事

Shackleford, B, Yasuda, M, Okushi, E, Koizumi, H, Tomiyama, H & Yasuura, H 1996, 'Satsuki: An integrated processor synthesis and compiler generation system', IEICE Transactions on Information and Systems, 巻. E79-D, 番号 10, pp. 1373-1381.
Shackleford B, Yasuda M, Okushi E, Koizumi H, Tomiyama H, Yasuura H. Satsuki: An integrated processor synthesis and compiler generation system. IEICE Transactions on Information and Systems. 1996;E79-D(10):1373-1381.
Shackleford, Barry ; Yasuda, Mitsuhiro ; Okushi, Etsuko ; Koizumi, Hisao ; Tomiyama, Hiroyuki ; Yasuura, Hiroto. / Satsuki : An integrated processor synthesis and compiler generation system. :: IEICE Transactions on Information and Systems. 1996 ; 巻 E79-D, 番号 10. pp. 1373-1381.
@article{1209e3fc598942dcb8a389243cc1b85e,
title = "Satsuki: An integrated processor synthesis and compiler generation system",
abstract = "Entire systems on a chip(SOCs)embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16word register file.",
author = "Barry Shackleford and Mitsuhiro Yasuda and Etsuko Okushi and Hisao Koizumi and Hiroyuki Tomiyama and Hiroto Yasuura",
year = "1996",
language = "English",
volume = "E79-D",
pages = "1373--1381",
journal = "IEICE Transactions on Information and Systems",
issn = "0916-8532",
publisher = "一般社団法人電子情報通信学会",
number = "10",

}

TY - JOUR

T1 - Satsuki

T2 - An integrated processor synthesis and compiler generation system

AU - Shackleford, Barry

AU - Yasuda, Mitsuhiro

AU - Okushi, Etsuko

AU - Koizumi, Hisao

AU - Tomiyama, Hiroyuki

AU - Yasuura, Hiroto

PY - 1996

Y1 - 1996

N2 - Entire systems on a chip(SOCs)embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16word register file.

AB - Entire systems on a chip(SOCs)embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16word register file.

UR - http://www.scopus.com/inward/record.url?scp=0030264191&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030264191&partnerID=8YFLogxK

M3 - Article

VL - E79-D

SP - 1373

EP - 1381

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

SN - 0916-8532

IS - 10

ER -