Short term cell-flipping technique for mitigating SNM degradation due to NBTI

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

1 引用 (Scopus)

抄録

Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor. When the PMOS transistor is biased to negative voltage, threshold voltage shifts to negatively. On the other hand, the threshold voltage recovers if the PMOS transistor is positively biased. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the dynamic stress and recovery condition. There are two important characteristics. One is a stress probability, which is defined as the rate that the PMOS transistor is negatively biased. The other is a stress and recovery cycle, which is defined as the switching interval of an SRAM value. In our observations, in order to mitigate the NBTI degradation, the stress probability should be small and the stress and recovery cycle should be shorter than 10msec. Based on the observations, we propose a novel cell-flipping technique, which makes the stress probability close to 50%. In addition, we show results of the case studies, which apply the cell-flipping technique to register file and cache memories.

元の言語英語
ページ(範囲)520-529
ページ数10
ジャーナルIEICE Transactions on Electronics
E94-C
発行部数4
DOI
出版物ステータス出版済み - 1 1 2011

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Static random access storage
Transistors
Threshold voltage
Degradation
Recovery
Cache memory
Negative bias temperature instability
Electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Short term cell-flipping technique for mitigating SNM degradation due to NBTI. / Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto.

:: IEICE Transactions on Electronics, 巻 E94-C, 番号 4, 01.01.2011, p. 520-529.

研究成果: ジャーナルへの寄稿記事

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