TY - GEN
T1 - Simultaneous optimization of memory configuration and code allocation for low power embedded systems
AU - Matsumura, Tadayuki
AU - Ishihara, Tohru
AU - Yasuura, Hiroto
PY - 2008
Y1 - 2008
N2 - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.
AB - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.
UR - http://www.scopus.com/inward/record.url?scp=56749090645&partnerID=8YFLogxK
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U2 - 10.1145/1366110.1366206
DO - 10.1145/1366110.1366206
M3 - Conference contribution
AN - SCOPUS:56749090645
SN - 9781595939999
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 403
EP - 406
BT - GLSVLSI 2008
T2 - GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
Y2 - 4 March 2008 through 6 March 2008
ER -