Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

研究成果: 著書/レポートタイプへの貢献会議での発言

4 引用 (Scopus)

抄録

This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

元の言語英語
ホスト出版物のタイトルGLSVLSI 2008
ホスト出版物のサブタイトルProceedings of the 2008 ACM Great Lakes Symposium on VLSI
ページ403-406
ページ数4
DOI
出版物ステータス出版済み - 12 1 2008
イベントGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, 米国
継続期間: 3 4 20083 6 2008

出版物シリーズ

名前Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

その他

その他GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
米国
Orlando, FL
期間3/4/083/6/08

Fingerprint

Embedded systems
Data storage equipment
Electric power utilization
Memory architecture
Degradation

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Matsumura, T., Ishihara, T., & Yasuura, H. (2008). Simultaneous optimization of memory configuration and code allocation for low power embedded systems. : GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (pp. 403-406). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1366110.1366206

Simultaneous optimization of memory configuration and code allocation for low power embedded systems. / Matsumura, Tadayuki; Ishihara, Tohru; Yasuura, Hiroto.

GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. 2008. p. 403-406 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

研究成果: 著書/レポートタイプへの貢献会議での発言

Matsumura, T, Ishihara, T & Yasuura, H 2008, Simultaneous optimization of memory configuration and code allocation for low power embedded systems. : GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 403-406, GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, FL, 米国, 3/4/08. https://doi.org/10.1145/1366110.1366206
Matsumura T, Ishihara T, Yasuura H. Simultaneous optimization of memory configuration and code allocation for low power embedded systems. : GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. 2008. p. 403-406. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1366110.1366206
Matsumura, Tadayuki ; Ishihara, Tohru ; Yasuura, Hiroto. / Simultaneous optimization of memory configuration and code allocation for low power embedded systems. GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. 2008. pp. 403-406 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).
@inproceedings{e0923e84bbd34ed8a9de68634bf575e1,
title = "Simultaneous optimization of memory configuration and code allocation for low power embedded systems",
abstract = "This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, {\ss}ratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8{\%} with 7.7{\%} memory array area overhead without degradations of SNM and access delay.",
author = "Tadayuki Matsumura and Tohru Ishihara and Hiroto Yasuura",
year = "2008",
month = "12",
day = "1",
doi = "10.1145/1366110.1366206",
language = "English",
isbn = "9781595939999",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
pages = "403--406",
booktitle = "GLSVLSI 2008",

}

TY - GEN

T1 - Simultaneous optimization of memory configuration and code allocation for low power embedded systems

AU - Matsumura, Tadayuki

AU - Ishihara, Tohru

AU - Yasuura, Hiroto

PY - 2008/12/1

Y1 - 2008/12/1

N2 - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

AB - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

UR - http://www.scopus.com/inward/record.url?scp=56749090645&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=56749090645&partnerID=8YFLogxK

U2 - 10.1145/1366110.1366206

DO - 10.1145/1366110.1366206

M3 - Conference contribution

AN - SCOPUS:56749090645

SN - 9781595939999

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 403

EP - 406

BT - GLSVLSI 2008

ER -