Soft-core processor architecture for embedded system design

Eko Fajar Nurprasetyo, Akihiko Inoue, Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: ジャーナルへの寄稿記事

17 引用 (Scopus)

抄録

In the design of an embedded system, an architecture of core processor strongly affects the performance and cost of the total system. This paper discusses a scalable processor architecture, called soft-core processor, which can be tuned for a target system. System designers can optimize several design parameters such as the datapath width and instruction set, and generate customized processors for their application. Design of Bung-DLX as a prototype of soft-core processor is presented in this paper. An experiment of system design using our processor has shown that the optimized processor chip area halves when the critical path delay is reduced to one third of the original one.

元の言語英語
ページ(範囲)1416-1422
ページ数7
ジャーナルIEICE Transactions on Electronics
E81-C
発行部数9
出版物ステータス出版済み - 1 1 1998

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Embedded systems
Systems analysis
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Nurprasetyo, E. F., Inoue, A., Tomiyama, H., & Yasuura, H. (1998). Soft-core processor architecture for embedded system design. IEICE Transactions on Electronics, E81-C(9), 1416-1422.

Soft-core processor architecture for embedded system design. / Nurprasetyo, Eko Fajar; Inoue, Akihiko; Tomiyama, Hiroyuki; Yasuura, Hiroto.

:: IEICE Transactions on Electronics, 巻 E81-C, 番号 9, 01.01.1998, p. 1416-1422.

研究成果: ジャーナルへの寄稿記事

Nurprasetyo, EF, Inoue, A, Tomiyama, H & Yasuura, H 1998, 'Soft-core processor architecture for embedded system design', IEICE Transactions on Electronics, 巻. E81-C, 番号 9, pp. 1416-1422.
Nurprasetyo EF, Inoue A, Tomiyama H, Yasuura H. Soft-core processor architecture for embedded system design. IEICE Transactions on Electronics. 1998 1 1;E81-C(9):1416-1422.
Nurprasetyo, Eko Fajar ; Inoue, Akihiko ; Tomiyama, Hiroyuki ; Yasuura, Hiroto. / Soft-core processor architecture for embedded system design. :: IEICE Transactions on Electronics. 1998 ; 巻 E81-C, 番号 9. pp. 1416-1422.
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