Soft-core processor architecture for embedded system design

Eko Fajar Nurprasetyo, Akihiko Inoue, Hiroyuki Tomiyama, Hiroto Yasuura

研究成果: Contribution to journalArticle査読

18 被引用数 (Scopus)

抄録

In the design of an embedded system, an architecture of core processor strongly affects the performance and cost of the total system. This paper discusses a scalable processor architecture, called soft-core processor, which can be tuned for a target system. System designers can optimize several design parameters such as the datapath width and instruction set, and generate customized processors for their application. Design of Bung-DLX as a prototype of soft-core processor is presented in this paper. An experiment of system design using our processor has shown that the optimized processor chip area halves when the critical path delay is reduced to one third of the original one.

本文言語英語
ページ(範囲)1416-1422
ページ数7
ジャーナルIEICE Transactions on Electronics
E81-C
9
出版ステータス出版済み - 1998

All Science Journal Classification (ASJC) codes

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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