抄録
Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.
| 元の言語 | 英語 |
|---|---|
| ページ（範囲） | 31-41 |
| ページ数 | 11 |
| ジャーナル | IEEE Design and Test of Computers |
| 巻 | 18 |
| 発行部数 | 2 |
| DOI | |
| 出版物ステータス | 出版済み - 3 1 2001 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
これを引用
Software energy reduction techniques for variable-voltage processors. / Okuma, Takanori; Yasuura, Hiroto; Ishihara, Tohru.
：: IEEE Design and Test of Computers, 巻 18, 番号 2, 01.03.2001, p. 31-41.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - Software energy reduction techniques for variable-voltage processors
AU - Okuma, Takanori
AU - Yasuura, Hiroto
AU - Ishihara, Tohru
PY - 2001/3/1
Y1 - 2001/3/1
N2 - Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.
AB - Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=0035280198&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0035280198&partnerID=8YFLogxK
U2 - 10.1109/54.914613
DO - 10.1109/54.914613
M3 - Article
AN - SCOPUS:0035280198
VL - 18
SP - 31
EP - 41
JO - IEEE Design and Test
JF - IEEE Design and Test
SN - 2168-2356
IS - 2
ER -