Software energy reduction techniques for variable-voltage processors

Takanori Okuma; Hiroto Yasuura; Tohru Ishihara

doi:10.1109/54.914613

Software energy reduction techniques for variable-voltage processors

Takanori Okuma, Hiroto Yasuura, Tohru Ishihara

総長・役員等

研究成果: ジャーナルへの寄稿 › 学術誌 › 査読

26 被引用数 (Scopus)

抄録

Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.

本文言語	英語
ページ（範囲）	31-41
ページ数	11
ジャーナル	IEEE Design and Test of Computers
巻	18
号	2
DOI	https://doi.org/10.1109/54.914613
出版ステータス	出版済み - 3月 2001

!!!All Science Journal Classification (ASJC) codes

ソフトウェア
ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/54.914613

他のファイルとリンク

引用スタイル

@article{d040bf56b2de4d278206f800d2d6e523,

title = "Software energy reduction techniques for variable-voltage processors",

abstract = "Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.",

author = "Takanori Okuma and Hiroto Yasuura and Tohru Ishihara",

year = "2001",

month = mar,

doi = "10.1109/54.914613",

language = "English",

volume = "18",

pages = "31--41",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "2",

}

TY - JOUR

T1 - Software energy reduction techniques for variable-voltage processors

AU - Okuma, Takanori

AU - Yasuura, Hiroto

AU - Ishihara, Tohru

PY - 2001/3

Y1 - 2001/3

N2 - Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.

AB - Voltage scheduling techniques for real-time applications using a variable-voltage processor are proposed. The techniques always guarantee satisfaction of a system's real-time constraints if the system meets those constraints under the highest supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=0035280198&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035280198&partnerID=8YFLogxK

U2 - 10.1109/54.914613

DO - 10.1109/54.914613

M3 - Article

AN - SCOPUS:0035280198

VL - 18

SP - 31

EP - 41

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 2

ER -

Software energy reduction techniques for variable-voltage processors

抄録

!!!All Science Journal Classification (ASJC) codes

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル