## 抄録

This paper presents new results on an approach for solving satisfiability problems (SAT), i.e. creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Arrays (FPGAs). This approach becomes feasible due to the recent advances in FPGAs and high-level logic synthesis. In this approach, each SAT problem is automatically analyzed and implemented on FPGAs. We have developed an algorithm which is suitable for implementing on a logic circuit. This algorithm is equivalent to the Davis-Putnam procedure with a powerful dynamic variable ordering heuristic. The algorithm does not have a large memory structure like a stack; thus sequential accesses to the memory do not become a bottleneck in algorithm execution. Simulation results show that this method can solve a hard random 3-SAT problem with 400 variables within 20 minutes at a clock rate of 1 MHz.

本文言語 | 英語 |
---|---|

ページ（範囲） | 179-186 |

ページ数 | 8 |

ジャーナル | Unknown Journal |

巻 | 7 |

出版ステータス | 出版済み - 1998 |

外部発表 | はい |

## All Science Journal Classification (ASJC) codes

- Software
- Industrial and Manufacturing Engineering