Stable Hysteresis-Free MoS2Transistors with Low-k/High-k Bilayer Gate Dielectrics

Zhijie Zhang, Meng Su, Guoli Li, Jianlu Wang, Xiaoyu Zhang, Johnny C. Ho, Chunlan Wang, Da Wan, Xingqiang Liu, Lei Liao

研究成果: Contribution to journalArticle査読

2 被引用数 (Scopus)

抄録

Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high-k property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to 7.0 × 1011 cm-2 C eV-1 and -2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.

本文言語英語
論文番号9109258
ページ(範囲)1036-1039
ページ数4
ジャーナルIEEE Electron Device Letters
41
7
DOI
出版ステータス出版済み - 7 2020
外部発表はい

All Science Journal Classification (ASJC) codes

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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