TY - JOUR
T1 - Stable Hysteresis-Free MoS2Transistors with Low-k/High-k Bilayer Gate Dielectrics
AU - Zhang, Zhijie
AU - Su, Meng
AU - Li, Guoli
AU - Wang, Jianlu
AU - Zhang, Xiaoyu
AU - Ho, Johnny C.
AU - Wang, Chunlan
AU - Wan, Da
AU - Liu, Xingqiang
AU - Liao, Lei
N1 - Funding Information:
Manuscript received May 19, 2020; accepted June 1, 2020. Date of publication June 5, 2020; date of current version June 29, 2020. This work was supported in part by the National Key Research and Development Program of Ministry of Science and Technology under Grant 2018YFA0703704 and Grant 2018YFB0406603, in part by the China National Funds for Distinguished Young Scientists under Grant 61925403, in part by the National Natural Science Foundation of China under Grant 61851403, Grant 61811540408, Grant 51872084, and Grant 61704051, in part by the Key Research and Development Plan of Hunan Province under Grant 2018GK2064, and in part by the Natural Science Foundation of Hunan Province under Grant 2017RS3021 and Grant 2017JJ3033. The review of this letter was arranged by Editor T. Palacios. (Zhijie Zhang and Meng Su contributed equally to this work.) (Corresponding authors: Xingqiang Liu; Lei Liao.) Zhijie Zhang and Meng Su are with the School of Physics and Technology, Wuhan University, Wuhan 430072, China.
Publisher Copyright:
© 1980-2012 IEEE.
PY - 2020/7
Y1 - 2020/7
N2 - Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high-k property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to 7.0 × 1011 cm-2 C eV-1 and -2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.
AB - Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high-k property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to 7.0 × 1011 cm-2 C eV-1 and -2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.
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U2 - 10.1109/LED.2020.3000259
DO - 10.1109/LED.2020.3000259
M3 - Article
AN - SCOPUS:85089530689
VL - 41
SP - 1036
EP - 1039
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 7
M1 - 9109258
ER -