The residual stress of the silicon die in an embedded die substrate was investigated. A silicon test element chip having piezo-resistance gauges was embedded in a printed circuit board substrate with the newly developed hollow chamber and laser-drilled slits around die technology. The embedded die was mechanically held with a copper redistribution layer (RDL), and dielectric epoxy resin remained at a part of the periphery. Slits of various designs were fabricated. The residual stresses near the center and a corner of the chip and their change with temperature were measured. The laser slits enabled to reduce the residual stress due to the difference in coefficient of thermal expansion (CTE) between materials.