Synthesis algorithm of parallel index generation units

研究成果: 著書/レポートタイプへの貢献会議での発言

3 引用 (Scopus)

抜粋

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generation units. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesis parallel index generation units. Experimental results show the proposed method outperforms other existing methods.

元の言語英語
ホスト出版物のタイトルProceedings - Design, Automation and Test in Europe, DATE 2014
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷物)9783981537024
DOI
出版物ステータス出版済み - 2014
イベント17th Design, Automation and Test in Europe, DATE 2014 - Dresden, ドイツ
継続期間: 3 24 20143 28 2014

その他

その他17th Design, Automation and Test in Europe, DATE 2014
ドイツ
Dresden
期間3/24/143/28/14

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • これを引用

    Matsunaga, Y. (2014). Synthesis algorithm of parallel index generation units. : Proceedings - Design, Automation and Test in Europe, DATE 2014 [6800511] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/DATE2014.310