Systematic design methodology of a wideband multibit continuous-time delta-sigma modulator

Awinash Anand, Nischal Koirala, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida

研究成果: ジャーナルへの寄稿記事

1 引用 (Scopus)

抄録

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 μm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

元の言語英語
記事番号275289
ジャーナルInternational Journal of Microwave Science and Technology
DOI
出版物ステータス出版済み - 4 3 2013

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Modulators
modulators
methodology
broadband
Operational amplifiers
clocks
dynamic range
Clocks
CMOS
topology
Topology
bandwidth
Bandwidth
Compensation and Redress

All Science Journal Classification (ASJC) codes

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

これを引用

Systematic design methodology of a wideband multibit continuous-time delta-sigma modulator. / Anand, Awinash; Koirala, Nischal; Pokharel, Ramesh; Kanaya, Haruichi; Yoshida, Keiji.

:: International Journal of Microwave Science and Technology, 03.04.2013.

研究成果: ジャーナルへの寄稿記事

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