Test architecture optimization for system-on-a-chip under floorplanning constraints

Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga

研究成果: ジャーナルへの寄稿記事

抄録

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

元の言語英語
ページ(範囲)3174-3184
ページ数11
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E87-A
発行部数12
出版物ステータス出版済み - 1 1 2004

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Floorplanning
Chip
Optimization
Locality
Wire
Architecture
Model

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

これを引用

Test architecture optimization for system-on-a-chip under floorplanning constraints. / Sugihara, Makoto; Murakami, Kazuaki; Matsunaga, Yusuke.

:: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 巻 E87-A, 番号 12, 01.01.2004, p. 3174-3184.

研究成果: ジャーナルへの寄稿記事

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