The architecture of OCMP and its evaluation

K. Saisho, T. Sano, Akira Fukuda

研究成果: Contribution to conferencePaper査読

抄録

By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two characteristics: one is the instruction level dispatching mechanism; and the other is the divided cache system. OCMP employs a fork-join type parallel processing model in order to simplify the dispatching mechanism. By dividing the cache system into shared cache and private cache, the cache coherence problem between processors on the same chip is removed and access conflict on the shared cache is also relaxed. OCMP is evaluated with the instruction level simulator developed by the authors. Two types of instruction level dispatching mechanisms are compared. The memory access mechanism is evaluated with various parameters such as memory access cost, the degree of simultaneous access to shared cache, and so on.

本文言語英語
ページ71-77
ページ数7
DOI
出版ステータス出版済み - 1 1 1997
外部発表はい
イベント3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997 - Taipei, 台湾省、中華民国
継続期間: 12 18 199712 20 1997

その他

その他3rd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 1997
国/地域台湾省、中華民国
CityTaipei
Period12/18/9712/20/97

All Science Journal Classification (ASJC) codes

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 安全性、リスク、信頼性、品質管理

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