A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.
|ホスト出版物のタイトル||Unknown Host Publication Title|
|出版物ステータス||出版済み - 1984|
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