TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

研究成果: 著書/レポートタイプへの貢献会議での発言

8 引用 (Scopus)

抄録

A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.

元の言語英語
ホスト出版物のタイトルUnknown Host Publication Title
出版者IEEE
ページ197-199
ページ数3
出版物ステータス出版済み - 1984
外部発表Yes

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Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Ishiura, N., Yasuura, H., & Yajima, S. (1984). TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.Unknown Host Publication Title (pp. 197-199). IEEE.

TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION. / Ishiura, Nagisa; Yasuura, Hiroto; Yajima, Shuzo.

Unknown Host Publication Title. IEEE, 1984. p. 197-199.

研究成果: 著書/レポートタイプへの貢献会議での発言

Ishiura, N, Yasuura, H & Yajima, S 1984, TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.Unknown Host Publication Title. IEEE, pp. 197-199.
Ishiura N, Yasuura H, Yajima S. TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION. : Unknown Host Publication Title. IEEE. 1984. p. 197-199
Ishiura, Nagisa ; Yasuura, Hiroto ; Yajima, Shuzo. / TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION. Unknown Host Publication Title. IEEE, 1984. pp. 197-199
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abstract = "A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.",
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N2 - A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.

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