TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

8 被引用数 (Scopus)

抄録

A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.

本文言語英語
ホスト出版物のタイトルUnknown Host Publication Title
出版社IEEE
ページ197-199
ページ数3
出版ステータス出版済み - 1984
外部発表はい

All Science Journal Classification (ASJC) codes

  • 工学(全般)

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