Triple line-based playout for Go - An accelerator for Monte Carlo Go

Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

1 被引用数 (Scopus)

抄録

After a computer named "Deep Blue" defeated the world chess champion Garry Kasparov in 1997, researchers studying computer board games focused their attention on the game "Go." Go is known to be more difficult for computers to play than chess or shogi because (1) the search space for Go is much larger, (2) it is difficult to define an appropriate evaluation function of position, and (3) a position sometimes changes globally in just one move. Recently, a new method called Monte Carlo Go has been developed, which involves performing Monte Carlo simulations to evaluate a position. Monte Carlo Go increases the strength of the Computer-Go program. For Monte Carlo Go, the strength fully depends on the number of simulations. Several attempts were made to accelerate simulations, e.g., by the use of cluster systems and FPGAs. The cluster system yields good results, but it is a very expensive system. On the other hand, acceleration using an FPGA was not so easy because the usage of FPGA resources tends to be high. Previously, FPGA acceleration was feasible for smaller board such as a board with a 9 x 9 grid, while it was not feasible for the standard board with a 19 x 19 grid. In this paper, we propose triple line-based playout for Go (TLPG), a hardware algorithm for generating simulations using an FPGA. By reproducing global information redundantly, TLPG enables the generation of simulations only using local operations; this helps realize compact implementations of hardware logic, and thus, TLPG can handle both 9 x 9 and 19 x 19 grid Go boards. We implement TLPG on Xilinx Virtex-5 (XC5VFX70T-1FF1136) and evaluate it. TLPG can perform 40,649 playouts per second for a 9 x 9 grid Go board and 4,668 playouts per second for a 19 x 19 grid Go board.

本文言語英語
ホスト出版物のタイトルReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs
ページ161-166
ページ数6
DOI
出版ステータス出版済み - 2009
外部発表はい
イベント2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09 - Cancun, メキシコ
継続期間: 12 9 200912 11 2009

出版物シリーズ

名前ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs

会議

会議2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09
国/地域メキシコ
CityCancun
Period12/9/0912/11/09

All Science Journal Classification (ASJC) codes

  • ハードウェアとアーキテクチャ
  • ソフトウェア

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