Variable ordering of binary decision diagrams for multi-level logic minimization

Masahiro Fujita, Yusuke Matsunaga

研究成果: Contribution to journalArticle査読

6 被引用数 (Scopus)

抄録

Binary Decision Diagram (BDD) is now widely used in CAD fields, especially in formal verification and logic synthesis. In this paper, variable ordering methods of BDD for the application of multi-level logic minimization are presented. The variable ordering algorithm for sum-of-products representation is based on cover patterns and selects most binary variables first, and the one for multi-level logic representation is based on depth first traversal of circuits. In both cases, the obtained variable orderings are optimized by exchanging a variable with its neighbor in the ordering. Experimental results show the effectiveness of our methods.

本文言語英語
ページ(範囲)137-145
ページ数9
ジャーナルFujitsu Scientific and Technical Journal
29
2
出版ステータス出版済み - 6 1 1993
外部発表はい

All Science Journal Classification (ASJC) codes

  • 人間とコンピュータの相互作用
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「Variable ordering of binary decision diagrams for multi-level logic minimization」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル