VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.

Kazuo Seo, Hiroshi Fujita

研究成果: 著書/レポートタイプへの貢献会議での発言

1 引用 (Scopus)

抄録

A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.

元の言語英語
ホスト出版物のタイトルUnknown Host Publication Title
出版者IEEE
ページ826-830
ページ数5
ISBN(印刷物)0818605638
出版物ステータス出版済み - 12 1 1984

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Extrapolation
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Seo, K., & Fujita, H. (1984). VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.Unknown Host Publication Title (pp. 826-830). IEEE.

VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. / Seo, Kazuo; Fujita, Hiroshi.

Unknown Host Publication Title. IEEE, 1984. p. 826-830.

研究成果: 著書/レポートタイプへの貢献会議での発言

Seo, K & Fujita, H 1984, VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.Unknown Host Publication Title. IEEE, pp. 826-830.
Seo K, Fujita H. VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. : Unknown Host Publication Title. IEEE. 1984. p. 826-830
Seo, Kazuo ; Fujita, Hiroshi. / VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. Unknown Host Publication Title. IEEE, 1984. pp. 826-830
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