### 抜粋

A high-speed multiplier suitable for VLSI implementation is proposed. The multiplier utilizes the redundant binary representation in internal computation and a redundant binary addition tree. In n-bit multiplication, n n-bit partial products are generated first and represented in the redundant binary representation. They are then added together pairwise by using a binary tree of redundant binary adders and the product in the redundant binary representation is obtained by the addition of left bracket log//2**n right bracket steps. In the redundant binary representation, since parallel addition of two numbers can be performed in a constant time independent of the number of digits of the operands, one can obtain the product in the redundant binary representation with a computing time proportional to log//2**n. Finally, the product is converted into the general binary representation. The n-bit multiplication can be performed in a computing time of 0(log**n) as a whole.

元の言語 | 英語 |
---|---|

ページ（範囲） | 19-28 |

ページ数 | 10 |

ジャーナル | Systems, computers, controls |

巻 | 14 |

発行部数 | 4 |

出版物ステータス | 出版済み - 1 1 1983 |

外部発表 | Yes |

### All Science Journal Classification (ASJC) codes

- Engineering(all)

## フィンガープリント VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE.' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

## これを引用

*Systems, computers, controls*,

*14*(4), 19-28.