A high-speed multiplier suitable for VLSI implementation is proposed. The multiplier utilizes the redundant binary representation in internal computation and a redundant binary addition tree. In n-bit multiplication, n n-bit partial products are generated first and represented in the redundant binary representation. They are then added together pairwise by using a binary tree of redundant binary adders and the product in the redundant binary representation is obtained by the addition of left bracket log//2**n right bracket steps. In the redundant binary representation, since parallel addition of two numbers can be performed in a constant time independent of the number of digits of the operands, one can obtain the product in the redundant binary representation with a computing time proportional to log//2**n. Finally, the product is converted into the general binary representation. The n-bit multiplication can be performed in a computing time of 0(log**n) as a whole.
|ジャーナル||Systems, computers, controls|
|出版物ステータス||出版済み - 1 1 1983|
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