Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

研究成果: 著書/レポートタイプへの貢献会議での発言

1 引用 (Scopus)

抜粋

We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

元の言語英語
ホスト出版物のタイトル2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
ページ135-136
ページ数2
DOI
出版物ステータス出版済み - 2006
外部発表Yes
イベント2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, 台湾省、中華民国
継続期間: 4 24 20064 26 2006

その他

その他2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
台湾省、中華民国
Hsinchu
期間4/24/064/26/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

これを引用

Watanabe, N., Kojima, T., & Asano, T. (2006). Wafer-level compliant bump for 3D chip-stacking. : 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers (pp. 135-136). [4016636] https://doi.org/10.1109/VTSA.2006.251100