Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

9 被引用数 (Scopus)

抄録

We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

本文言語英語
ホスト出版物のタイトルIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
ページ671-674
ページ数4
出版ステータス出版済み - 12 1 2005
イベントIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, 米国
継続期間: 12 5 200512 7 2005

出版物シリーズ

名前Technical Digest - International Electron Devices Meeting, IEDM
2005
ISSN(印刷版)0163-1918

その他

その他IEEE International Electron Devices Meeting, 2005 IEDM
Country米国
CityWashington, DC, MD
Period12/5/0512/7/05

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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