Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Naoya Watanabe; Takeaki Kojima; Tanemasa Asano

Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

集積電子システム

研究成果: Chapter in Book/Report/Conference proceeding › Conference contribution

9 被引用数 (Scopus)

抄録

We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

本文言語	英語
ホスト出版物のタイトル	IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
ページ	671-674
ページ数	4
出版ステータス	出版済み - 12 1 2005
イベント	IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, 米国継続期間: 12 5 2005 → 12 7 2005

出版物シリーズ

名前	Technical Digest - International Electron Devices Meeting, IEDM
巻	2005
ISSN（印刷版）	0163-1918

その他

その他	IEEE International Electron Devices Meeting, 2005 IEDM
Country	米国
City	Washington, DC, MD
Period	12/5/05 → 12/7/05

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

フィンガープリント「Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル

Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections. / Watanabe, Naoya; Kojima, Takeaki; Asano, Tanemasa.

IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. 2005. p. 671-674 1609440 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).

研究成果: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, N, Kojima, T & Asano, T 2005, Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections. in IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest., 1609440, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2005, pp. 671-674, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, 米国, 12/5/05.

@inproceedings{f4fec8e34c4e4e6882f0b89f336da8b2,

title = "Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections",

abstract = "We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.",

author = "Naoya Watanabe and Takeaki Kojima and Tanemasa Asano",

year = "2005",

month = dec,

day = "1",

language = "English",

isbn = "078039268X",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "671--674",

booktitle = "IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest",

note = "IEEE International Electron Devices Meeting, 2005 IEDM ; Conference date: 05-12-2005 Through 07-12-2005",

}

TY - GEN

T1 - Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

AU - Watanabe, Naoya

AU - Kojima, Takeaki

AU - Asano, Tanemasa

PY - 2005/12/1

Y1 - 2005/12/1

N2 - We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

AB - We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

UR - http://www.scopus.com/inward/record.url?scp=33847726635&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847726635&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33847726635

SN - 078039268X

SN - 9780780392687

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 671

EP - 674

BT - IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest

T2 - IEEE International Electron Devices Meeting, 2005 IEDM

Y2 - 5 December 2005 through 7 December 2005

ER -