TY - GEN
T1 - Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections
AU - Watanabe, Naoya
AU - Kojima, Takeaki
AU - Asano, Tanemasa
PY - 2005/12/1
Y1 - 2005/12/1
N2 - We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.
AB - We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.
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M3 - Conference contribution
AN - SCOPUS:33847726635
SN - 078039268X
SN - 9780780392687
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 671
EP - 674
BT - IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
T2 - IEEE International Electron Devices Meeting, 2005 IEDM
Y2 - 5 December 2005 through 7 December 2005
ER -